Static-random-access memory (SRAM) cells typically have a four transistor or a six transistor configuration. FIG. 1 includes a circuit diagram of a four transistor SRAM cell 10 that has two pass transistors 11 and 14, two latch transistors 12 and 15, and two load resistors 13 and 16. The electrical connection of the pass transistor 11, latch transistor 12, and load resistor 13 forms a first storage node 17, and the electrical connection of the pass transistor 14, latch transistor 15, and load resistor 16 forms a second storage node 18. Electrical connections are made to the SRAM cell 10 and include a word line 19, two bit lines having complementary signals (BL and BL), and V.sub.SS and V.sub.DD. FIG. 2 includes a circuit diagram of a six transistor SRAM cell 20 that is similar to SRAM cell 10 except that load resistors 13 and 16 are replaced by load transistors 23 and 26 and have gate electrodes that are connected to the storage nodes 18 and 17, respectively. Transistors 11, 12, 14, and 15 are n-channel transistors, and transistors 23 and 26 are p-channel transistors.
Before continuing with the background, a couple of terms need be understood. A channel region has a physical width and an effective (or electrical) width. The physical width is the width of the active or channel region as measured by the distance between field isolation regions (i.e., field oxide). To determine the effective width of a channel region, both an area of channel inversion region and an effective length of the channel region are determined by electrical measurements. The effective length of the channel region is about the distance between the source and drain regions under a gate electrode. The length of the channel region is measured in the direction in which electrons (or holes) typically flow through the channel region. The effective width of the channel region is the quotient of the area of channel inversion divided by the effective length of the channel region. The effective width is influenced by the lateral diffusion of the channel-stop dopants. In general, the physical width is the distance between the field isolation regions, and the effective width is about the distance between channel-stop regions.
Each of the pass and latch transistors 11, 12, 14, and 15 has a gain associated with its transistor. With the SRAM cell 10, the gain of the latch transistors 12 and 15 are typically designed to be at least three times greater than the gain of the pass transistors 11 and 14. The ratio of the gains is called the "beta ratio" and should be at least 3:1. The beta ratio is a function of the channel lengths and widths of the latch and pass transistors. One way to achieve a beta ratio of 3:1 is to make the quotient of the physical channel width divided by the physical channel length of the latch transistors at least three times larger than the quotient of the physical channel width divided by the physical channel length of the pass transistors. Using symbols, EQU ((W/L).sub.latch :(W/L).sub.pass).gtoreq.3:1
Such a requirement makes the designing of a small SRAM cell difficult because the contact area (determined by W.sub.pass) for the bit line connections may become too small. Also, the field oxidation process may limit how narrow a channel width may become due to minimum lithographic features as dictated by the dimensions of the mask.
Another attempt to achieve higher beta ratio is to place small resistive sections between the pass transistors 11 and 14 and their associated storage nodes 17 and 18. A special mask is typically needed to achieve this result, but the resistance is expected to be sensitive to virtually any mask misalignment.
In another attempt to increase the beta ratio, different gate oxide layer thicknesses may be used for the latch and pass transistors. The process for forming the gate oxide layers typically forms a thicker gate oxide layer for the pass transistors compared to the latch transistors. The thicker gate oxide layer may cause the threshold voltages for the pass and latch transistors to be different. Also, extra processing steps are needed to form the gate oxide layers. Usually, the thicker oxide layer is formed first and the thinner oxide layer is formed second. When removing the thicker gate oxide layer from the location where the latch transistors are formed, a masking layer (photoresist) is formed over the thicker gate oxide layer where the pass transistors are formed. The thicker gate oxide layer may become contaminated during these extra processing steps and degrade device reliability.